The present invention relates generally to electronic devices and more particularly to improved trim circuitry and methods for trimming electronic devices.
Trim circuits are found in many types of electrical devices where a voltage, current, or other operational parameter of a device needs to be adjusted, either during or following manufacturing. Such trim circuitry typically provides a resistance between two nodes in an integrated circuit device, which may be selectively removed, in whole or in part, from the circuit upon application of voltages or currents to trim pads in the device. Trim circuits often employ zener diodes connected in parallel with the resistor to be removed, where the application of an appropriate trim voltage across the diode terminals short-circuits the resistor, sometimes referred to as xe2x80x9cblowingxe2x80x9d the diode.
In other trim circuits, open-circuits may be selectively created so as to adjust the device performance. In this instance, fuses are often formed in the trim circuit, which can be selectively open circuited by conducting a fuse trim current through the fuse, sometimes referred to as xe2x80x9cblowingxe2x80x9d the fuse. Such trim circuits, including fuse types and diode types, find application in a wide variety of electrical devices. For instance, trim circuits are often employed in voltage reference or regulator devices wherein one or more reference voltages generated by the device are adjusted during the manufacturing process, such as prior to packaging individual devices.
Many such trim cells may be cascaded in serial fashion, whereby incremental adjustment (e.g., reduction) in the overall resistance may be achieved by sequentially applying such voltages across the diodes to selectively remove incremental resistances from the overall circuit. Such circuits are sometimes referred to as multi-bit trim circuits. For example, a series of such cells, each having a resistor connected in parallel with a zener diode, may be formed in an electrical device between two nodes of interest. An operational parameter associated with the device is measured, and a decision is made as to whether the device needs to be trimmed. If so, one of the diodes is blown, thereby shorting a corresponding one of the series resistors between the device nodes. The device is re-measured, and if further trimming or adjustment of the operating parameter is needed, the process repeats, with further diodes being blown so as to remove further resistance.
A conventional zener diode type trim cell 2 is illustrated in FIGS. 1A-1C, consisting of a resistor 4 and a zener diode 6 connected in parallel between two trim pads A and B. FIGS. 1A and 1C illustrate the trim cell 2 prior to the diode 6 being shorted, and FIG. 1B schematically illustrates the cell 2 after the diode has been sacrificially destroyed by application of a trim voltage across the pads A and B. The structural view of the trim cell 2 in FIG. 1C illustrates the layout of the pads A, B, the diode 6 and the resistor 4 in a portion of a typical electrical device semiconductor substrate 10, where the resistor 4 includes a resistor tank or portion 12 formed in the substrate 10. The tank 12 may be formed by selectively doping the tank portion 12 with a dopant which is different from the dopant type in the surrounding portions of the substrate 10. For instance, the tank 12 may be doped with P+ dopants where the surrounding substrate 10 is N type. Conductive contacts 14 and 16 are formed to electrically connect first and second ends of the tank 12 of the resistor 4 to the pads A and B, respectively.
The zener diode 6 consists of a similar tank region 18 doped with the same type dopant used in the resistor tank 12, and a second region 20 formed in the tank 18 by doping with a dopant of a different type. For example, the diode tank 18 is commonly doped with P type impurities while the second region 20 is doped with N type impurities. The edges of the second region 20 thus form a PN junction of the diode 6 at the interfaces between the P doped material of the tank 18 and the N type material in the second region 20. The N type doped material in the second region 20 (e.g., the cathode of the diode 6) is electrically connected to the pad B via an electrical contact 22, and the opposite end of the diode tank 18 (e.g., the anode) is connected to the pad A via a contact 24, wherein the contacts 14, 16, 22, 24 and the pads A, B are commonly formed in a metalization layer during fabrication of an electrical device (not shown) of which the trim cell 2 is a part.
In operation, the resistor 4 provides an electrical resistance between the pads A, B, which may be connected to nodes in a circuit (not shown). If it is determined that the electrical resistance needs to be removed, a voltage is applied (e.g., in either direction) across the pads A, B of sufficient level to cause heating of conductive metal near the second region 20 of the diode 6. For instance, where a DC voltage is applied with pad A held more negative than pad B, a field is established between the contact 22 at the second diode region 20 and the contact 24 at the opposite end of the diode tank 18. Conductive material (e.g., metal) from the contact 22 melts and spikes through the PN junction of the diode 6, and migrates through the tank 18 toward the contact 24, eventually shorting out the diode 6. This, in turn, short-circuits the resistor 4 in the resistor tank 12, whereby the electrical resistance of the resistor 4 is effectively removed from the circuit between the pads A and B, as illustrated schematically in FIG. 1B.
It is noted in FIG. 1C that the conventional trim cell 2 occupies a relatively large amount of area in the substrate 10. This is due at least in part to the separate tanks 12, 18 used to form the resistor 4 and the diode 6, respectively. As device densities continue to increase and device sizes and spacings continue to decrease in the design of modern semiconductor devices, the real estate in the substrate 10 becomes more and more costly. Accordingly, it is desirable to provide improved trim cell designs which take up less space in integrated circuits, while allowing the selective removal of electrical resistance therefrom.
Another shortcoming with conventional trim cell architectures is found where multiple cells 2 are configured in serial fashion to allow so-called multi-bit trimming. It is noted in FIG. 1A that the two pads A, B must be electrically accessed (e.g., probed) in order to remove the resistance of the resistor 4 (e.g., by blowing the diode 6) in the trim cell 2. Thus, where N such trim cells are configured in series, N+1 pads are needed to allow selective access for trimming the individual cells 2, each of which occupies a significant amount of surface area. Thus, it is also desirable to provide multi-bit trim cells occupying less overall real estate than the series configuration of multiple conventional trim cells such as that illustrated in FIGS. 1A-1C.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides single and multiple bit trim cells by which electrical resistance can be selectively removed from an electrical circuit in a controlled fashion without occupying excessive amounts of space in an electrical device. Trimming circuitry is provided comprising a resistor and a diode formed in the resistor body having a conductive portion selectively melted to short the resistor. The resistor may be formed in a bipolar process, such as during formation of bipolar transistor base structures, with the diode formed while constructing transistor emitter structures in the device. A multi-bit trim cell is also provided having two or more trim cells or circuits individually comprising a resistor with a diode formed in the resistor body for selectively shorting the resistor, and a fuse for selectively disconnecting the diode from a trim pad, wherein multiple trim cells may be trimmed using a single pair of trim pads. In addition, the invention provides methods and systems for trimming electrical devices to selectively remove resistance between two nodes in a device.
In accordance with one aspect of the invention, a trim circuit is provided, which comprises a resistor and a diode, the resistor providing an electrical resistance between first and second nodes in an electrical device. A first end of the resistor is connected to the first node and to a first pad in the electrical device. The diode comprises an anode, a cathode, and a conductive portion with the anode connected to the second end of the resistor, and the cathode connected to a second pad in the electrical device. Thus, the resistor and diode of the present invention are not connected in parallel, as was the case in the conventional trim cell 2 of FIG. 1A-1C above. Application of a trim voltage across the pads causes the conductive portion of the diode to electrically connect the ends of the resistor to thereby remove resistance between the first and second nodes.
In one implementation, the trim voltage causes melting of the conductive diode portion and spiking of conductive material through a PN junction of the diode formed in a resistor body, with the melted material being distributed or displaced along the length of the resistor body so as to short-circuit the resistor. The trim circuit may further comprise a fuse connected between the cathode and the second pad. A trim current may be applied between the pads to open circuit the fuse, thereby disconnecting the cathode from the second pad following short-circuiting of the resistor. In this manner, the application of the trim voltage removes electrical resistance between the first and second nodes, and application of the trim current disconnects the second pad from the first and second nodes.
According to another aspect of the invention, a multi-bit trim circuit is provided having two or more trim cells providing selectively removable resistances connected in series between two nodes in an electrical device. The trim circuit may be operated by application of signals to a single pair of terminals to selectively remove one or more of the series resistances. In this manner, the invention provides multi-bit trimming capabilities, which may be implemented to occupy less die area than was the case with conventional multi-bit trim circuits. In addition, the invention allows such multi-bit trimming via a single pair of pads. Thus, where such pads are accessible on a packaged device, the invention facilitates post-packaging trim operations.
This aspect provides multi-bit trim circuits comprising a first trim cell connected to a first node and to first and second pads in the electrical device, and at least a second trim cell connected between the first trim cell and the second node. The trim cells individually comprise a resistor with a resistor body and a diode formed in the resistor body. The resistor body extends in a substrate between first and second ends and provides an electrical resistance between the first and second nodes, where the diode comprises a conductive portion connecting a cathode to the second pad. Application of a trim voltage across the pads causes the conductive portion of the diode to connect the first and second ends of the resistor so as to remove resistance between the first and second nodes. The trim cells may further comprise a fuse connected between the cathode and the second pad, which selectively disconnects the cathode from the second pad after a trim current is applied between the first and second pads.
Other aspects of the invention provide systems and methods for trimming an electrical device to selectively remove resistance between two nodes in the device. The method comprises applying a trim voltage across first and second pads in the electrical device to short a first resistor in a first trim cell between the two nodes, and applying a trim current between the first and second pads to disconnect the first trim cell from the second pad. Thereafter a determination is made as to whether additional trimming is desired. If so, the application of the trim voltage and the trim current is repeated so as to remove further resistance between the two nodes.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.